Typical semiconductor devices include metal conductors or traces and vias for electrically coupling portions of the semiconductor devices. One method for creating these metal conductors uses a damascene fill process. The process includes forming fine pitch lines by laser structuring a dielectric layer, overfilling the structured dielectric layer by a copper electroplating process, and back etching the excess copper to expose the structured dielectric layer and the trace structures.
This damascene fill process requires a uniform, planar copper plating process. As such, the deposited copper layer must be very flat and uniform to enable etchback and singulation of the metal traces. The uniform deposition process, however, only works for very fine structures. Due to the electroplating process characteristics with copper deposition on the sidewalls of the fine structures, the copper growth is such that the copper surface above the fine structures is almost flat. This does not work for larger structures, however, therefore a dent is visible in the area of larger structures. When the copper is etched back to expose the underlying structures, the copper in the large structures will be etched out completely. Therefore, this process is not capable of creating relatively large structure elements, such as land pads for solder balls.
For these and other reasons, there is a need for the present invention.